X
X
R
R
P
P
7
7
7
7
0
0
8
8
a
a
n
n
d
d
X
X
R
R
P
P
7
7
7
7
4
4
0
0
Q
Q
u
u
a
a
d
d
C
C
h
h
a
a
n
n
n
n
e
e
l
l
D
D
i
i
g
g
i
i
t
t
a
a
l
l
P
P
W
W
M
M
S
S
t
t
e
e
p
p
D
D
o
o
w
w
n
n
C
C
o
o
n
n
t
t
r
r
o
o
l
l
l
l
e
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r
s
s
?2012 Exar Corporation
18/28
Rev. 1.2.2
CHIP OPERATION AND CONFIGURATION
SOFT-START
The SET_SS_RISE_CHx register is a 16 bit register which specifies the soft-start delay and the
ramp characteristics for a specific channel. This register allows the customer to program the
channel with a 250us step resolution and up to a maximum 16ms delay.
Bits [15:10] specify the delay after enabling a channel but before outputting pulses; where each bit
represents 250us steps. Bits [9:0] specify the rise time of the channel; these 10 bits define the
number of microseconds for each 50mV increment to reach the target voltage. The status of the
soft-start operation is indicated in the POWER_GOOD_SOFT_START_FLAG register by bits [3:0]
which correspond to channels 4 though 1 respectively. A value of 1 signifies that a soft start is in
operation on a given channel.
Enable
Signal
Vout
SS_RISE_CHx
REGISTER
Bit [0:9]
RISE TIME
DELAY
Bit [10:15]
Fig. 20: Channel Power Up Sequence
SOFT-STOP
The SET_PD_FALL_CHx register is a 16 bit register. This register specifies the soft-stop delay and
ramp (fall-time) characteristics for when the chip receives a channel disable indication from the
Host to shutdown the channel.
Bits [15:10] specify the delay after disabling a channel but before starting the shutdown of the
channel; where each bit represents 250us steps. Bits [9:0] specify the fall time of the channel;
these 10 bits define the number of microseconds for each 50mV increment to reach the discharge
threshold.
DELAY
Fall Time
Bit [10:15]
Bit [0:9]
Vout
Enable
Signal
PD_DELAY_CHx
REGISTER
Fig. 23: Channel Soft-Stop Sequence
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